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? semiconductor components industries, llc, 2010 march, 2018 ? rev. 3 1 publication order number: fan53555/d fan53555 5 a, 2.4 mhz, digitally programmable tinybuck ? regulator description the fan53555 is a step ? down switching voltage regulator that delivers a digitally programmable output from an input voltage supply of 2.5 v to 5.5 v. the output voltage is programmed through an i 2 c interface capable of operating up to 3.4 mhz. using a proprietary architecture with synchronous rectification, the fan53555 is capable of delivering 5 a continuous at over 80% efficiency, while maintaining over 80% efficiency at load currents as low as 10 ma. pulse currents as high as 6.5 a can be supported by the 05 option. the regulator operates at a nominal fixed frequency of 2.4 mhz, which reduces the value of the external components to 330 nh for the output induction and as low as 20 f for the output capacitor. additional output capacitance can be added to improve regulation during load transients without affecting stability. inductance up to 1.2 h may be used with additional output capacitance. at moderate and light loads, pulse frequency modulation (pfm) is used to operate in power ? save mode with a typical quiescent current of 60 a. even with such a low quiescent current, the part exhibits excellent transient response during large load swings. at higher loads, the system automatically switches to fixed ? frequency control, operating at 2.4 mhz. in shutdown mode, the supply current drops below 1 a, reducing power consumption. pfm mode can be disabled if constant frequency is desired. the f an53555 is available in a 20 ? bump, 1.6 x 2 mm, wlcsp. features ? fixed ? frequency operation: 2.4 mhz ? best ? in ? class load transient ? continuous output current capability: 5 a ? pulse current capability: 6.5 a (05 option) ? 2.5 v to 5.5 v input voltage range ? digitally programmable output voltage: ? 00/01/03/05/08/18 options: 0.6 ? 1.23 v in 10 mv steps ? 04/042/09/ options: 0.603 ? 1.411 v in 12.826 mv steps ? 23, 79 option: 0.60 ? 1.3875 v in 12.5 mv steps ? 24 option: 0.603 ? 1.420 v in 12.967 mv steps ? 13 option: 0.8 ? 1.43 v in 10 mv steps ? programmable slew rate for voltage transitions ? i 2 c ? compatible interface up to 3.4 mbps ? pfm mode for high efficiency in light load ? quiescent current in pfm mode: 60 a (typical) ? internal soft ? start ? input under ? voltage lockout (uvlo) ? thermal shutdown and overload protection ? 20 ? bump wafer ? level chip scale package (wlcsp) applications ? application, graphic, and dsp processors arm ? , krait, omap?, novathor?, armada ? hard disk drives ? tablets, netbooks, ultra ? mobile pcs ? smart phones ? gaming devices figure 1. typical application fan53555 sw c out l1 pvin gnd c in vout c in1 agnd core processor (system load) gnd vdd vsel scl sda en www. onsemi.com
fan53555 www. onsemi.com 2 table 1. ordering information part number power ? up defaults i 2 c slave address a1 pin function max. r c ms cur- rent max. pulse current (50 ms) programmable output voltage en pin low vsel0 vsel1 fan53555uc00x 1.05 1.20 c0 vsel 5 a n/a 0.6 ? 1.23 v in 10mv registers not reset fan53555uc01x 0.90 off vsel 5 a n/a fan53555uc03x 0.90 n/a pgood 5 a n/a fan53555uc04x 1.10 1.20 vsel 5 a n/a 0.603 ? 1.411 v in 12.826mv registers reset fan53555uc05x 0.90 off vsel 5 a 6.5 a 0.6 ? 1.23 v in 10mv registers not reset fan53555buc05x (note 1) 0.90 off vsel 5 a 6.5 a fan53555uc08x 1.02 1.15 vsel 4 a n/a fan53555buc08x (note 1) 1.02 1.15 vsel 4 a n/a fan53555buc09x (note 1) 1.10 1.10 vsel 3 a n/a 0.603 ? 1.411 v in 12.826mv fan53555uc09x 1.10 1.10 vsel 3 a n/a fan53555uc13x 1.15 1.15 vsel 5 a n/a 0.8 ? 1.43 v in 10mv fan53555buc13x (note 1) 1.15 1.15 vsel 5 a n/a FAN53555UC18X 1.02 1.15 vsel 5 a n/a 0.6 ? 1.23 v in 10mv fan53555buc18x (note 1) 1.02 1.15 vsel 5 a n/a fan5355buc79x 0.85 n/a pgood 5 a n/a registers reset fan53555buc23x (note 1) 1.15 1.15 vsel 5 a n/a 0.6 ? 1.3875 v in 12.5mv registers not reset fan53555uc24x 1.225 1.212 vsel 4 a n/a 0.603 ? 1.42 v in 12.967mv registers reset fan53555buc24x (note 1) 1.225 1.212 vsel 4 a n/a fan53555uc042x (note 2) 1.10 1.20 c4 vsel 5 a n/a 0.603 ? 1.411 v in 12.826mv 1. the fan53555buc05x, fan53555buc08x, fan53555buc09x, fan53555buc13x, fan53555buc18x, fan53555buc23x, and fan53555buc24x, include backside lamination. 2. the 042 option is the same as the 04 option, except the i 2 c slave addresses. 3. temperature range ? 40 to 85 c, package wlcsp ? 20, packing method tape & reel
fan53555 www. onsemi.com 3 recommended external components table 2. recommended external components for 5 a maximum load current component description vendor parameter typ. unit l1 330 nh nominal see table 3 l 0.33 h dcr 13 m c out 2 pieces; 22 f, 6.3 v, x5r, 0805 grm21br60j226m (murata) c2012x5r0j226m (tdk) c 44 f c in 1 piece; 10 f, 10 v, x5r, 0805 lmk212bj106kg ? t (taiyo yuden) c2012x5r1a106m (tdk) c 10 2 pieces; 10 f, 6.3 v, x5r, 0805 grm21br60j106m (murata) c2012x5r0j106m (tdk) c 20 c in1 10 nf, 25 v, x7r, 0402 grm155r71e103k (murata) c1005x7r1e103k (tdk) c 10 nf table 3. recommended inductors for high ? current applications manufacturer part# l (nh) dcr (m ) i maxdc (note 4) component dimensions l w h vishay ihlp1616aberr47m01 470 20 .0 5 .0 4.5 4.1 1.2 mag . layers (note 5) mmd ? 04abnr33m ? m1 ? ru 330 12.5 7.5 4.5 4.1 1.2 mag . layers mmd ? 04abnr47m ? m1 ? ru 470 20 .0 5 .0 4.5 4.1 1.2 inter ? technical sm1608 ? r33m 33 0 9.6 9 .0 4.5 4.1 2.0 bournes srp4012 ? r33m 330 15 .0 6.7 4.7 4.2 1.2 bournes srp4012 ? r47m 470 20 .0 5 .0 4.7 4.2 1.2 tdk vlc5020t ? r47m 470 15 .0 5.4 5.0 5.0 2.0 4. i maxdc is the lesser current to produce 40 c temperature rise or 30% inductance roll ? off. 5. preferred inductor value is 330 nh and all dynamic characterization was performed with this coil. fan53555 ? 24, ? 08, and ? 09 reduced output current (4 a max. rms. for 08, and 24, 3 a max. rms for 09) smaller footprint application the fan53555 ? 24, ? 08, and ? 09 were developed to provide power for core processors with high ? performance graphics acceleration in li ? ion ? powered handheld devices. these applications require a very compact solution. the smaller input and output capacitors in the table below assume that additional bypass capacitance exists across the battery in fairly close proximity to the regulator(s). the c in capacitors specified below are the capacitors that are required in very close proximity to vin and pgnd (see layout recommendations in figure 2 below) . table 4. recommended external components for lower ? current applications with fan53555 ? 08 ? 09 ? 24 component description vendor parameter typ unit l1 470 or 330 nh, 2016 case size see table 5 c out ? 08, ,24 option 2 pieces 22 f, 6.3 v, x5r, 0603 c1608x5r0j226m (tdk) c 44 f ? 09 option 1 piece 22 f, 6.3 v, x5r, 0603 22 c in 1 piece; 10 f, 10 v, x5r, 0402 grm155r61a106m (murata) c 10 c in1 10 nf, 25 v, x5r, 0201 tmk063cg100dt ? f (taiyo yuden) c 10 nf
fan53555 www. onsemi.com 4 table 5. recommended inductors for lower ? current applications with fan53555 ? 08 ? 09 ? 24 manufacturer part# l (nh) dcr (m typ . ) i maxdc (note 6) component dimensions l w h toko dfe201612r - h ? r33n 330 25 3.2 2.0 1.6 1.2 toko dfe201612c ? r47n 470 40 3.2 2.0 1.6 1.2 cyntek pife20161b ? r47ms ? 39 470 30 3.1 2.0 1.6 1.2 semco cigt201610hmr47sce 470 30 3.1 2.0 1.6 0.9 6. i maxdc is the lesser current to produce 40 c temperature rise or 30% inductance roll ? off. layout en scl vout vin sw vsel* gnd c1 a1 a2 c3 b3 a3 c2 d1 d3 d2 b2 c4 b4 a4 d4 e1 e3 e2 e4 agnd sda a1 = vsel for 00, 01, 04, 05, 08, 09, 13, 18, 23, 24 a1 = pgood for 03 79 , c1 b1 a1 c3 b3 a3 a2 c2 d1 d3 d2 b2 c4 b4 a4 d4 e1 e3 e2 e4 b1 figure 2. reduced ? footprint layout figure 3. top view pin configuration table 6. pin definitions pin # name description a1 vsel (except ? 03 option) voltage select. when this pin is low, v out is set by the vsel0 register. when this pin is high, v out is set by the vsel1 register. pgood (03) power good. this open ? drain pin pulls low if an overload condition occurs or soft ? start is in progress. a2 en enable. the device is in shutdown mode when this pin is low. all register values are kept during shut- down. options 00, 01, 03, 05, 08 09, 13, 18, and 23 do not reset register values when en is raised. the 04, 24, 79, and 042 options reset all registers to default values when en pin is low. if pulled up to a low ? im- pedance voltage source greater than 1.8 v, use at least 100 series resistor. a3 scl i 2 c serial clock a4 vout vout. sense pin for vout. connect to cout. b1 sda i 2 c serial data b2, b3, c1 ? c4 gnd ground. low ? side mosfet is referenced to this pin. c in and c out should be returned with a minimal path to these pins. b4 agnd analog ground. all signals are referenced to this pin. avoid routing high dv/dt ac currents through this pin.
fan53555 www. onsemi.com 5 table 6. pin definitions pin # description name d1, d2, e1, e2 vin power input voltage. connect to the input power source. connect to c in with minimal path. d3, d4, e3, e4 sw switching node. connect to the inductor. table 7. absolute maximum ratings symbol parameter min max unit v in voltage on sw, vin pins ic not switching ? 0.3 7.0 v ic switching ? 0.3 6.5 voltage on en pin tied without series resistance ) ? 0.3 2.0 v tied through series resistance of at least 100 ? 0.3 v in (note 7) voltage on all other pins ic not switching ? 0.3 v in (note 7) v v out voltage on vout pin ? 0.3 3.0 v v inov_slew maximum slew rate of v in > 6.5 v, pwm switching 100 v/ms esd electrostatic discharge protection level human body model per jesd22 ? a114 2000 v charged device model per jesd22 ? c101 1500 t j junction temperature ? 40 +150 c t stg storage temperature ? 65 +150 c t l lead soldering temperature, 10 seconds +260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 7. lesser of 7 v or v in +0.3 v. table 8. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. on semiconductor does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min typ max unit v in supply voltage range 2.5 5.5 v i out output current 0 5 a l inductor 0.33 h c in input capacitor 10 f c out output capacitor 44 f t a operating ambient temperature ? 40 +85 c t j operating junction temperature ? 40 +125 c table 9. thermal properties symbol parameter min typ max unit ja junction ? to ? ambient thermal resistance (note 8) 38 c/w 8. see thermal considerations in the application information section.
fan53555 www. onsemi.com 6 table 10. electrical characteristics minimum and maximum values are at v in = 2.5 v to 5.5 v, t a = ? 40 c to +85 c, unless otherwise noted. typical values are at t a = 25 c, v in = 5 v, and en = high. symbol parameter condition min typ max unit power supplies i q quiescent current i load =0 60 100 a i load =0, mode bit=1 (forced pwm) 43 ma i sd h/w shutdown supply current en=gnd 0.1 5.0 a s/w shutdown supply current en= v in , buck_enx=0 41 75 a v uvlo under ? voltage lockout threshold v in rising 2.35 2.45 v v uvhyst under ? voltage lockout hysteresis 350 mv en, vsel, sda, scl v ih high ? level input voltage 1.1 v v il low ? level input voltage 0.4 v v lhyst logic input hysteresis voltage 160 mv i in input bias current input tied to gnd or vin 0.01 1.00 a pgood (03, 79 option) i outl pgood pull ? down current 1 ma i outh pgood high leakage current 0.01 1.00 a v out regulation v reg v out dc accuracy i out(dc) =0, forced pwm, v out =vsel0 default value ? 1.5 1.5 % 08, 24 op- tions 2.5 v v in 4.5 v, v out from minimum to maximum, i out(dc) =0 to 4 a, auto pfm/pwm ? 2.0 4.0 % 09 option 2.5 v v in 4.5 v, v out from minimum to maximum, i out(dc) =0 to 3 a, auto pfm/pwm ? 2.0 4.0 % 13, 18, 23 options 2.5 v v in 4.5 v, v out from minimum to maximum, i out(dc) =0 to 5 a, auto pfm/pwm ? 2.0 4.0 % all other options 2.5 v v in 5.5 v, v out from minimum to maximum, i out(dc) =0 to 5 a, auto pfm/pwm ? 3.0 5.0 % load out i v load regulation i out(dc) =1 to 5 a ? 0.1 %/a line regulation 2.5 v v in 5.5 v, i out(dc) =1.5 a 0.01 %/v in out v v v trsp transient response i load step 0.1 a to 1.5 a, t r =t f =100 ns, v out =1.2 v 40 mv continued on the following page power switch and protection r ds(on)p p ? channel mosfet on resistance v in =5 v 28 m r ds(on)n n ? channel mosfet on resistance v in =5 v 17 m
fan53555 www. onsemi.com 7 table 10. electrical characteristics minimum and maximum values are at v in = 2.5 v to 5.5 v, t a = ? 40 c to +85 c, unless otherwise noted. typical values are at t a = 25 c, v in = 5 v, and en = high. symbol unit max typ min condition parameter power switch and protection i limpk p ? mos peak current limit 00, 01, 03, 04, 13, 18, 23, 042, 79 options 6.3 7.4 8.5 a 05 option 8.5 10.0 11.5 a 08, 24 options 5.0 5.9 6.8 a 09 option 4.0 4.75 5.5 t limit thermal shutdown 150 c t hyst thermal shutdown hysteresis 17 c v sdwn input ovp shutdown rising threshold 6.15 v falling threshold 5.50 5.85 v frequency control f sw oscillator frequency 2.05 2.40 2.75 mhz dac resolution 6 bits differential nonlinearity ( 9 ) 0.5 lsb timing i 2 c en en=high to i 2 c start 100 s soft ? start t ss regulator enable to regulated v out r load > 5 ; to v out =1.2 v; 00, 01, 03, 04, 042, 05, 09, 13, 23 and 79 options 300 s 2.5 v v in 4.5 v; r load =2 ; to v out =1.127 v with 1.1 v pre ? bias volt- age; 08 and 18 options 135 175 s r off vout pull ? down resistance, dis- abled en=0 or v in fan53555 www. onsemi.com 8 table 11. i 2 c timing specifications guaranteed by design. symbol unit max. typ. min. condition parameter t low scl low period standard mode 4.7 s fast mode 1.3 s fast mode plus 0.5 s high ? speed mode, c b 100 pf 160.0 ns high ? speed mode, c b 400 pf 320.0 ns t high scl high period standard mode 4 s fast mode 600 ns fast mode plus 260 ns high ? speed mode, c b 100 pf 60 ns high ? speed mode, c b 400 pf 120 ns t su;sta repeated start setup time standard mode 4.7 s fast mode 600.0 ns fast mode plus 260.0 ns high ? speed mode 160.0 ns t su;dat data setup time standard mode 250 ns fast mode 100 fast mode plus 50 high ? speed mode 10 t hd;dat data hold time standard mode 0 3.45 s fast mode 0 900.00 ns fast mode plus 0 450.00 ns high ? speed mode, c b 100 pf 0 70.00 ns high ? speed mode, c b 400 pf 0 150.00 ns t rcl scl rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 80 high ? speed mode, c b 400 pf 20 160 t fcl scl fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 40 high ? speed mode, c b 400 pf 20 80 t rcl1 rise time of scl after a repeated start condition and after ack bit high ? speed mode, c b 100 pf 10 80 ns high ? speed mode, c b 400 pf 20 160 t rda sda rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 80 high ? speed mode, c b 400 pf 20 160
fan53555 www. onsemi.com 9 table 11. i 2 c timing specifications guaranteed by design. symbol unit max. typ. min. condition parameter t fda sda fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high ? speed mode, c b 100 pf 10 80 high ? speed mode, c b 400 pf 20 160 t su;sto stop condition setup time standard mode 4 s fast mode 600 ns fast mode plus 120 ns high ? speed mode 160 ns c b capacitive load for sda and scl 400 pf timing diagrams ?? start ?? ?? ?? ?? ?? ?? ???? ???? ??? ?? figure 4. i 2 c interface timing for fast plus, fast, and slow modes ???? ???? repeated start ??? ??? ?? ?? ? up = r p resistor pull ? up note a note a: first rising edge of sclh after repeated start and after each ack bit. t hd;sta t su;sta figure 5. i 2 c interface timing for high ? speed mode
fan53555 www. onsemi.com 10 typical characteristics unless otherwise specified, auto pfm/pwm, v in = 3.6 v, v out = 1.2 v, scl = sda = vsel = en = 1.8 v, t a = 25 c; circuit and components according to figure 1 and table 1. 76% 78% 80% 82% 84% 86% 88% 90% 92% 0 1000 2000 3000 4000 5000 efficency load current (ma) 60% 65% 70% 75% 80% 85% 90% 0 1000 2000 3000 4000 5000 60% 65% 70% 75% 80% 85% 90% 0 1000 2000 3000 4000 5000 6000 7000 3.6vin, 1.2vout, l=mmd ? 04abnr33m 3.6vin, 1.2vout, l=vlc5020t ? r47m 5.0vin, 1.2vout, l=mmd ? 04abnr33m 5.0vin, 1.2vout, l=vlc5020t ? r47m 5.0vin, 0.9vout, l=mmd ? 04abnr33m 5.0vin, 0.9vout, l=vlc5020t ? r47m figure 6. efficiency vs. load current and input voltage 2.7 vin 3.6 vin 5.0 vin 76% 78% 80% 82% 84% 86% 88% 90% 92% 0 1000 2000 3000 4000 5000 efficency load current (ma) ? 40 c +25 c +85 c figure 7. efficiency vs. load current and temperature 70% 72% 74% 76% 78% 80% 82% 84% 86% 88% 90% efficency load current (ma) figure 8. efficiency vs. load current and input voltage, v out = 0.9 v 0 1000 2000 3000 4000 5000 70% 72% 74% 76% 78% 80% 82% 84% 86% 88% 90% efficency load current (ma) 0 1000 2000 3000 4000 5000 figure 9. efficiency vs. load current and temperature, v in = 5 v, v out = 1.2 v 2.7 vin 3.6 vin 5.0 vin ? 40 c +25 c +85 c efficency load current (ma) figure 10. efficiency vs. load current and input voltage, v out = 0.6 v efficency load current (ma) figure 11. efficiency vs. load current, v in = 3.6 v and 5 v, v out = 1.2 v and 0.9 v 2.7 vin 3.6 vin 5.0 vin
fan53555 www. onsemi.com 11 typical characteristics (continued) unless otherwise specified, auto pfm/pwm, v in = 3.6 v, v out = 1.2 v, scl = sda = vsel = en = 1.8 v, t a = 25 c; circuit and components according to figure 1 and table 1. 0 5 10 15 20 25 0 1000 2000 3000 4000 5000 0 4 8 12 16 20 0 1000 2000 3000 4000 5000 200 400 600 800 1,000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 200 400 600 800 1,000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 0 1000 2000 3000 4000 5000 0 500 1,000 1,500 2,000 2,500 3,000 0 1000 2000 3000 4000 5000 vout shift (mv) load current (ma) 2.7 vin 3.6 vin 5.0 vin figure 12. output regulation vs. load current and input voltage, v out = 1.2 v figure 13. output regulation vs. load current and input voltage, v out =0.9 v load current (ma) 2.7 vin 3.6 vin 5.0 vin pfm exit pfm enter laod current (ma) input voltage (v) figure 14. pfm entry / exit level vs. input voltage, v out =1.2 v pfm exit pfm enter load current (ma) input voltage (v) figure 15. pfm entry / exit level vs. input voltage, v out =0.9 v 3.6vin, 1.2vout, auto 3.6vin, 1.2vout, pwm 5.0vin, 1.2vout, auto 5.0vin, 1.2vout, pwm 5.0vin, 0.9vout, auto output ripple (mvpp) load current (ma) figure 16. output ripple vs. load current, v in =5 v and 3.6 v, v out =1.2 v and 0.9 v, auto and fpwm 3.6vin, 1.2vout, auto 3.6vin, 0.9vout, auto 5.0vin, 1.2vout, auto 5.0vin, 0.9vout, auto figure 17. frequency vs. load current, v in =5 v and 3.6 v, v out =1.2 v and 0.9 v, auto pwm switching frequency (khz) load current (ma)
fan53555 www. onsemi.com 12 typical characteristics (continued) unless otherwise specified, auto pfm/pwm, v in = 3.6 v, v out = 1.2 v, scl = sda = vsel = en = 1.8 v, t a = 25 c; circuit and components according to figure 1 and table 1. 20 30 40 50 60 70 80 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 10 20 30 40 50 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 20 30 40 50 60 70 10 100 1,000 10,000 100k input supply voltage (v) input supply current ( a) figure 18. quiescent current vs. input voltage and temperature, auto pwm input voltage (v) input current (ma) ? 40 c +25 c +85 c ? 40 c +25 c +85 c figure 19. quiescent current vs. input voltage and temperature, fpwm 0 10 20 30 40 50 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 en_buck=0, ? 40c en_buck=0, +25c en_buck=0, +85c en=0, +25c input current ( a) input voltage (v) 3.6vin, 1.2vout, 2a load 3.6vin, 0.9vout, 2a load 5.0vin, 0.9vout, 18ma load, pfm pssr (db) frequency (hz) figure 20. shutdown current vs. input voltage and temperature figure 21. psrr vs. frequency figure 22. line transient, 3 ? 4 v in , 1.2 v out , 10 s edge, 50 load figure 23. line transient, 3 ? 4 v in , 1.2 v out , 10 s edge, 1 a load
fan53555 www. onsemi.com 13 typical characteristics (continued) unless otherwise specified, auto pfm/pwm, v in = 3.6 v, v out = 1.2 v, scl = sda = vsel = en = 1.8 v, t a = 25 c; circuit and components according to figure 1 and table 1. figure 24. load transient, 5 v in , 0.9 v out , 0.3 ? 3 a, 100 ns edge figure 25. load transient, 3.6 v in , 1.2 v out , 0.3 ? 3 a, 100 ns edge figure 26. load transient, 3.6 v in , 1.2 v out , 0.3 ? 3 a, 100 ns edge, c out =4x22 f figure 27. load transient, 3.6 v in , 1.2 v out , 1.5 ? 6 a, 100 ns edge, c out =4x22 f figure 28. input over ? voltage protection
fan53555 www. onsemi.com 14 typical characteristics (continued) unless otherwise specified, auto pfm/pwm, v in = 3.6 v, v out = 1.2 v, scl = sda = vsel = en = 1.8 v, t a = 25 c; circuit and components according to figure 1 and table 1. figure 29. startup / shutdown, no load, v out =0.9 v figure 30. startup / shutdown, 180 m load, v out =0.9 v figure 31. overload protection and recovery figure 32. startup into faulted load, v out =0.9 v operation description the fan53555 is a step ? down switching voltage regulator that delivers a programmable output voltage from an input voltage supply of 2.5 v to 5.5 v. using a proprietary architecture with synchronous rectification, the fan53555 is capable of delivering 5 a at over 80% efficiency. pulse currents as high as 6.5 a can be supported by the 05 option. the regulator operates at a nominal frequency of 2.4 mhz at full load, which reduces the value of the external components to 330 nh for the output inductor and 22 f for the output capacitor. high efficiency is maintained at light load with single ? pulse pfm. the fan53555 integrates an i 2 c ? compatible interface, allowing transfers up to 3.4 mbps. this communication interface can be used to: ? dynamically re ? program the output voltage in 10 mv, 12.826 mv increments (option 04, 09, and 042), 12.5 mv increments (option 23), or 12.967 mv increments (option 24); ? reprogram the mode to enable or disable pfm; ? control voltage transition slew rate; or ? enable / disable the regulator. control scheme the fan53555 uses a proprietary non ? linear, fixed ? frequency pwm modulator to deliver a fast load transient response, while maintaining a constant switching frequency over a wide range of operating conditions. the regulator performance is independent of the output capacitor esr, allowing for the use of ceramic output capacitors. although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency loop holds the switching frequency constant over a large range of input voltages and load currents. for very light loads, the fan53555 operates in discontinuous current diode (dcm) single ? pulse pfm,
fan53555 www. onsemi.com 15 which produces low output ripple compared with other pfm architectures. transition between pwm and pfm is relatively seamless, providing a smooth transition between dcm and ccm modes. pfm can be disabled by programming the mode bit high in the vsel registers. enable and soft ? start when the en pin is low; the ic is shut down, all internal circuits are off, and the part draws very little current. in this state, i 2 c cannot be written to or read from. for all options except the 04, 24, and 042 options, all register values are kept while en pin is low. for the 04, 24 042 and 79 options; registers are reset to default values when en pin is low. for all options, registers are reset to default values during a power on reset (por). when the output_discharge bit in the control register is enabled (logic high) and the en pin is low or the buck_enx bit is low, a load is connected from vout to gnd to discharge the output capacitors. raising en while the buck_enx bit is high activates the part and begins the soft ? start cycle. during soft ? start, the modulator?s internal reference is ramped slowly to minimize surge currents on the input and prevent overshoot of the output voltage. synchronous rectification is inhibited during soft ? start, allowing the ic to start into a pre ? charged capacitive load. if large output capacitance values are used, the regulator may fail to start. maximum c out capacitance for successfully starting with a heavy constant ? current load is approximately: c outmax i limpk i load 320 v out (eq. 1) where c outmax is expressed in f and i load is the load current during soft ? start, expressed in a. if the regulator is at its current limit for 16 consecutive current limit cycles, the regulator shuts down and enters 3 ? state before reattempting soft ? start 1700 ms later. this limits the duty cycle of full output current during soft ? start to prevent excessive heating. the ic allows for software enable of the regulator, when en is high, through the buck_en bits. buck_en0 and buck_en1 are both initialized high in the 00, 04, 08, 09, 23, 24, 42 and 79 options. these options start after a por regardless of the state of the vsel pin. in the 01 and 05 options, buck_en0 and buck_en1 are initialized to 10. using these options, vsel must be low after a por if the ic is powering the processor used to communicate through i 2 c. the 03 option has the vsel input to the modulator logic internally tied low. table 12. hardware and software enable pins bits output en vsel buck_en0 buck_en1 0 x x x off 1 0 0 x off 1 0 1 x on 1 1 x 0 off 1 1 x 1 on vsel pin and i 2 c programming output voltage the output voltage is set by the nselx control bits in vsel0 and vsel1 registers. the output voltage for options 00, 01, 03, 05, 08, 18 and 79 is given as: v out 0.60 v nselx 10 mv (eq. 2) for example, when nsel = 01 1111 (31 decimal), then v out = 0.60 + 0.310 = 0.91 v. v out 0.603 nselx 12.826 mv (eq. 3) for the 04, 042, and 09 options; the output voltage is given as: for the 13 option, the output voltage is given as: v out 0.80 nselx 10 mv (eq. 4)
fan53555 www. onsemi.com 16 for the 23 option, the output voltage is given as: v out 0.60 v nselx 12.5 mv (eq. 5) for the 24 option, the output voltage is given as: v out 0.603 v nselx 12.967 mv (eq. 6) output voltage can also be controlled by toggling the vsel pin low or high. vsel low corresponds to vsel0 and vsel high corresponds to vsel1. upon por, vsel0 and vsel1 are reset to their default voltages, shown in table 9. transition slew rate limiting when transitioning from a low to high voltage, the ic can be programmed for one of eight possible slew rates using the slew bits in the control register. table 13. transition slew rate decimal bin slew rate 0 000 64.00 mv / s 1 001 32.00 mv / s 2 01 0 16.00 mv / s 3 011 8.00 mv / s 4 100 4.00 mv / s 5 101 2.00 mv / s 6 110 1.00 mv / s 7 111 0.50 mv / s transitions from high to low voltage rely on the output load to discharge v out to the new set point. once the high ? to ? low transition begins, the ic stops switching until v out has reached the new set point. for options 04, 042, 09, 23, and 24 where the dynamic voltage scaling (dvs) step is not 10 mv; the actual slew rate is the corresponding number shown in table 6 scaled by the ratio of the dvs step to 10 mv. for example, the slew rate of option 13 for bin=011 is 8.00 mv / s x 12.5 mv / 10 mv = 10.00 mv / s. under ? voltage lockout when en is high, the under ? voltage lockout keeps the part from operating until the input supply voltage rises high enough to properly operate. this ensures proper operation of the regulator during startup or shutdown. input over ? voltage protection (ovp) when v in exceeds v sdwn (about 6.2 v) the ic stops switching to protect the circuitry from internal spikes above 6.5 v. an internal filter prevents the circuit from shutting down due to noise spikes. power good (03 & 79 option) the pgood pin is an open ? drain output indicating that the regulator is enabled when its state is high. pgood pulls low under the following conditions: ? regulator is disabled (en pin low, disabled by i 2 c, fault time ? out, uvlo, ovp, over ? temperature); ? regulator is performing a soft ? start. pgood remains high during i 2 c initiated v out transitions. current limiting a heavy load or short circuit on the output causes the current in the inductor to increase until a maximum current threshold is reached in the high ? side switch. upon reaching this point, the high ? side switch turns off, preventing high currents from causing damage. sixteen consecutive current limit cycles in current limit cause the regulator to shut down and stay off for about 1700 s before attempting a restart. thermal shutdown when the die temperature increases, due to a high load condition and/or high ambient temperature, the output switching is disabled until the die temperature falls sufficiently. the junction temperature at which the thermal shutdown activates is nominally 150 c with a 17 c hysteresis. monitor register (reg05) the monitor register indicates of the regulation state of the ic. if the ic is enabled and is regulating, its value is (1000 0000). i 2 c interface the fan53555?s serial interface is compatible with standard, fast, fast plus, and hs mode i 2 c ? bus specifications. the f an53555?s scl line is an input and its sda line is a bi ? directional open ? drain output; it can only pull down the bus when active. the sda line only pulls low during data reads and when signaling ack. all data is shifted in msb (bit 7) first. i 2 c slave address in hex notation, the slave address assumes a 0 ls bit. the hex slave address is c0 for all options except ? 42, which has a hex slave address of c4. table 14. i 2 c slave address option hex bits 7 6 5 4 3 2 1 0 00 to 24, 79 c0 1 1 0 0 0 0 0 w r/ 42 c4 1 1 0 0 0 1 0 w r/ other slave addresses can be assigned. contact a on semiconductor representative. bus timing as shown in , data is normally transferred when scl is low. data is clocked in on the rising edge of scl.
fan53555 www. onsemi.com 17 typically, data transitions shortly at or after the falling edge of scl to allow ample time for the data to set up before the next scl rising edge. scl t su t h sda data change allowed figure 33. data transfer timing each bus transaction begins and ends with sda and scl high. a transaction begins with a st art condition, which is defined as sda transitioning from 1 to 0 with scl high, as shown in . scl t hd;sta sda slave address ms bit figure 34. start bit a transaction ends with a stop condition, which is defined as sda transitioning from 0 to 1 with scl high, as shown in . scl sda slave releases master drives ack(0) or nack(1) t hd;sto figure 35. stop bit during a read from the fan53555, the master issues a repeated start after sending the register address, and before resending the slave address. the repeated start is a 1 to 0 transition on sda while scl is high, as shown in . scl sda ack(0) or nack(1) slave releases sladdr ms bit t hd;sta t su;sta figure 36. repeated start timing high ? speed (hs) mode the protocols for high ? speed (hs), low ? speed (ls), and fast ? speed (fs) modes are identical, except the bus speed for hs mode is 3.4 mhz. hs mode is entered when the bus master sends the hs master code 00001xxx after a start condition. the master code is sent in fast or fast ? plus mode (less than 1 mhz clock); slaves do not ack this transmission. the master generates a repeated start condition () that causes all slaves on the bus to switch to hs mode. the master then sends i 2 c packets, as described above, using the hs mode clock rate and timing. the bus remains in hs mode until a stop bit () is sent by the master. while in hs mode, packets are separated by repeated start conditions (). read and write transactions the following figures outline the sequences for data read and write. bus control is signified by the shading of the packet, defined as master drives bus and slave drives buss. all addresses and data are msb first. table 15. i 2 c bit definitions for figure 38 and figure 39 symbol definition r repeated start, see figure 37 p stop, see figure 36 s start, see figure 35 a ack. the slave drives sda to 0 to acknowledge the preceding packet. a nack. the slave sends a 1 to nack the pre- ceding packet. r repeated start, see figure 37 . p stop, see figure 36 . s slave address a reg addr a a p 0 7 bits 8 bits 8 bits data 000 figure 37. write transaction s slave address a reg addr a 0 7 bits 8 bits r slave address 7 bits 1 a data a 8 bits 00 01 p figure 38. read transaction
fan53555 www. onsemi.com 18 register description table 16. register map hex address name function por default option v out binary hex 00 vsel0 controls v out settings when vsel pin = 0 00 1.05 0 10101101 ad 08, 18 1.020 10101010 aa 01, 03, 05 0.90 0 10011110 9e 04, 1.10 0 10100111 a7 24 1.225 10110000 b0 13 1.150 10100011 a3 23 1.150 10101100 ac 09 1.100 10100111 a7 79 0.85 10011001 99 01 vsel1 controls v out settings when vsel pin = 1 00 1.20 0 11111100 fc 01, 05 1.00 0 01101000 68 04, 1.20 0 11101111 ef 24 1.212 10101111 af 08, 18 1.150 10110111 b7 13 1.150 10100011 a3 23 1.150 10101100 ac 09 1.100 11100111 e7 02 control determines whether v out output discharge is en- abled and also the slew rate of positive transitions 00, 01, 03, 04, 05, 24 10000000 80 08, 09, 18 00000000 00 13, 23 10110000 b0 03 id1 read ? only register identifies vendor and chip type 00 , 13, 23, 24 10000000 80 01 10000001 81 03 10000011 83 04 10000100 84 05 10000101 85 08, 18 10001000 88 09 10001100 8c 04 id2 read ? only register identifies die revision all 0000xxxx 0 x 05 monitor indicates device status all x0000000 x0 table 17. bit definitions the following table defines the operation of each register bit. bold indicates power ? on default values. bit name value description vsel0 r/w register address: 00 7 buck_en0 1 software buck enable. when en pin is low, the regulator is off. when en pin is high, buck_en bit takes precedent. 6 mode0 0 allow auto ? pfm mode during light load. 1 forced pwm mode.
fan53555 www. onsemi.com 19 table 17. bit definitions the following table defines the operation of each register bit. bold indicates power ? on default values. bit description value name vsel0 r/w register address: 00 5:0 nsel0 00 option 101101 sets v out value from 0.6 to 1.23 v in 10 mv steps (see eq. (2)). 08, 18 options 101010 01, 03, 05 options 011110 79 option 011001 04 option 100111 sets v out value from 0.603 to 1.411 v in 12.826 mv steps (see eq. (3)). 09 option 100111 13 option 100011 sets v out value from 0.8 to 1.43 v in 10 mv steps (see eq. (4)). 23 option 101100 sets v out value from 0.6 to 1.3875 v in 12.5 mv steps (see eq. (5)). 24 option 110000 sets v out value from 0.603 to 1.42 v in 12.967 mv steps (see eq. (6)). vsel1 r/w register address: 01 7 buck_en1 00, 04, 08, 09 , 13, 18, 23, 24 options 1 software buck enable. when en pin is low, the regulator is off. when en pin is high, buck_en bit takes precedent. 01, 05 options 0 6 mode1 08, 13, 18, 23, 24 options 0 allow auto ? pfm mode during light load. 00, 01, 04, 05, 09 options 1 forced pwm mode. 5:0 nsel1 00 option 111100 sets v out value from 0.6 to 1.23 v in 10 mv steps (see eq. (2)). 01, 05 options 101000 08, 18 options 110111 04 option 101111 sets v out value from 0.603 to 1.411 v in 12.826 mv steps (see eq. (3)). 09 option 100111 13 option 100011 sets v out value from 0.8 to 1.43 v in 10 mv steps (see eq. (4)). 23 option 010100 sets v out value from 0.6 to 1.3875 v in 12.5 mv steps (see eq. (5)). 24 option 101111 sets v out value from 0.603 to 1.42 v in 12.967 mv steps (see eq. (6)). control r/w register address: 02
fan53555 www. onsemi.com 20 table 17. bit definitions the following table defines the operation of each register bit. bold indicates power ? on default values. bit description value name control r/w register address: 02 7 output_discharge 08, 09, 18, 79 options 0 when the regulator is disabled, v out is not discharged. 00, 01, 03, 04, 05 , 13, 23, 24 options 1 when the regulator is disabled, v out discharges through an internal pull ? down. 6:4 slew 000 ?111 sets the slew rate for positive voltage transitions (see table 6). 011 default value for 13 and 23 options 3 reserved 0 always reads back 0 2 04, 09, 24, 79 options reset 0 setting to 1 resets all registers to default values. all other options reserved 0 always reads back 0 1:0 reserved 00 always reads back 00 id1 r register address: 03 7:5 vendor 100 signifies on semiconductor as the ic vendor 4 reserved 0 always reads back 0 3:0 die_id 0000 ic type = 00 option (fan53555uc00x / fan53555buc24x) 0001 ic type = 01 option (fan53555uc01x/ fan5355buc79x) 0011 ic type = 03 option (fan53555uc03x) 0100 ic type = 04 option (fan53555uc04x) 0100 ic type = 042 option (fan53555uc042x) 0101 ic type = 05 option (fan53555uc05x / fan53555buc05x) 1000 ic type = 08, 18 options (fan53555uc08x / fan53555buc08x, FAN53555UC18X / fan53555buc18x) 1100 ic type = 09 option (fan53555uc09x / fan53555buc09x) 0000 ic type = 13 option (fan53555uc13x / fan53555buc13x) 0000 ic type = 23 option (fan53555buc23x) id2 r register address: 04 7:4 reserved 0000 always reads back 0000
fan53555 www. onsemi.com 21 table 17. bit definitions the following table defines the operation of each register bit. bold indicates power ? on default values. bit description value name id1 r register address: 03 3:0 die_rev 00 option 0011 ic mask revision 01 option 0011 03 option 0011 04 option 1111 24 ? option 0100 0 42 option 1111 0 5 option 0011 0 8, 18 options 000 1 buc08, buc18 options 1111 09 option 1111 13 option 1111 23 option 11 00 79 option 1000 monitor r register address: 05 7 pgood 0 1: buck is enabled and soft ? start is completed 6:0 not used 000 0000 always reads back 000 0000 application information selecting the inductor the output inductor must meet both the required inductance and the energy ? handling capability of the application. the inductor value affects the average current limit, the output voltage ripple, and the efficiency. the ripple current ( i) of the regulator is: i v out v in v in v out l f sw (eq. 7) the maximum average load current, i max(load), is related to the peak current limit, i lim(pk) , by the ripple current such that: i max(load) i lim(pk) i 2 (eq. 8) the fan53555 is optimized for operation with l=330 nh, but is stable with inductances up to 1.0 h (nominal). the inductor should be rated to maintain at least 80% of its value at i lim(pk) . failure to do so lowers the amount of dc current the ic can deliver. efficiency is af fected by the inductor dcr and inductance value. decreasing the inductor value for a given physical size typically decreases the dcr; but since i increases, the rms current increases, as do core and skin ? effect losses. i rms i out(dc) 2 i 2 12 (eq. 9) the increased rms current produces higher losses through the r ds(on) of the ic mosfets as well as the inductor esr. increasing the inductor value produces lower rms currents, but degrades transient response. for a given
fan53555 www. onsemi.com 22 physical inductor size, increased inductance usually results in an inductor with lower saturation current. table 18. effects of inductor value (from 330 nh recommended) on regulator performance i max(load) v out (eq.(11)) transient response increase decrease degraded inductor current rating the current limit circuit can allow substantial peak currents to flow through l1 under worst ? case conditions. if it is possible for the load to draw such currents, the inductor should be capable of sustaining the current or failing in a safe manner. for space ? constrained applications, a lower current rating for l1 can be used. the fan53555 may still protect these inductors in the event of a short circuit, but may not be able to protect the inductor from failure if the load is able to draw higher currents than the dc rating of the inductor. output capacitor and v out ripple table 1 suggests 0805 capacitors, but 0603 capacitors may be used if space is at a premium. due to voltage effects, the 0603 capacitors have a lower in ? circuit capacitance than the 0805 package, which can degrade transient response and output ripple. increasing c out has negligible effect on loop stability and can be increased to reduce output voltage ripple or to improve transient response. output voltage ripple, v out , is calculated by: v out i l
f sw c out esr 2 2 d ( 1 d ) 1 8 f sw c out (eq. 10) where c out is the effective output capacitance. the capacitance of c out decreases at higher output voltages, which results in higher v out . equation (10) is only valid for continuous current mode (ccm) operation, which occurs when the regulator is in pwm mode. for large c out values, the regulator may fail to start under a load. if an inductor value greater than 1.0 h is used, at least 30 f of c out should be used to ensure stability. the lowest v out is obtained when the ic is in pwm mode and, therefore, operating at 2.4 mhz. in pfm mode, f sw is reduced, causing v out to increase. esl effects the equivalent series inductance (esl) of the output capacitor network should be kept low to minimize the square ? wave component of output ripple that results from the division ratio c out esl and the output inductor (l out ). the square ? wave component due to the esl can be estimated as: v out(sq) v in esl cout l1 (eq. 11) a good practice to minimize this ripple is to use multiple output capacitors to achieve the desired c out value. for example, to obtain c out =20 f, a single 22 f 0805 would produce twice the square wave ripple as two x 10 f 0805. to minimize esl, try to use capacitors with the lowest ratio of length to width. 0805s have lower esl than 1206s. if low output ripple is a chief concern, some vendors produce 0508 or 0612 capacitors with ultra ? low esl. placing additional small ? value capacitors near the load also reduces the high ? frequency ripple components. input capacitor the ceramic input capacitors should be placed as close as possible between the vin pin and pgnd to minimize the parasitic inductance. if a long wire is used to bring power to the ic, additional ?bulk? capacitance (electrolytic or tantalum) should be placed between c in and the power source lead to reduce under ? damped ringing that can occur between the inductance of the power source leads and c in . the effective c in capacitance value decreases as v in increases due to dc bias effects. this has no significant impact on regulator performance. thermal considerations heat is removed from the ic through the solder bumps to the pcb copper. the junction ? to ? ambient thermal resistance ( ja ) is largely a function of the pcb layout (size, copper weight, and trace width) and the temperature rise from junction to ambient ( t). for the fan53555uc, ja is 38 c/w when mounted on its four ? layer evaluation board in still air with two ? ounce outer layer copper weight and one ? ounce inner layers. halving the copper thickness results in an increased ja of 48 c/w. for long ? term reliable operation, the ic?s junction temperature (t j ) should be maintained below 125 c. to calculate maximum operating temperature (< 125 c) for a specific application: 1. use efficiency graphs to determine efficiency for the desired v in , v out , and load conditions. 2. calculate total power dissipation using: p t v out i load 1 1 (eq. 12) where is efficiency from figure 7 through figure 12. 3. estimate inductor copper losses using: p l i load 2 dcr l (eq. 13) 4. determine ic losses by removing inductor losses (step 3) from total dissipation: p ic p t p l (eq. 14) 5. determine device operating temperature: t p ic szie 7ja (eq. 15) and t ic t a t (eq. 16)
fan53555 www. onsemi.com 23 it is important to note that the r ds(on) of the ic?s power mosfets increases linearly with temperature at about 1.21%/ c. this causes the efficiency ( ) to degrade with increasing die temperature. layout recommendation figure 39. guidance for layer 1 figure 40. guidance for layer 2
fan53555 www. onsemi.com 24 figure 41. guidance for layer 3 1. fb trace connects to ?+? side of cout cap. 2. max trace resistance between fan53555 and cpu should not exceed 30m 3. do not place cout near fan53555, place cap near load length should be less than 0.5 inches width (mils) length (mils) copper (oz) resistance (m ) 25 500 2 4.2 25 500 1.5 4.9 25 500 1 5.8 25 500 0.5 7.6 table provides resistance values for given copper oz . figure 42. remote sensing schematic
fan53555 www. onsemi.com 25 figure 43. remote sensing guidance, top layer table 19. product ? specific dimensions product d e x y land pattern fan53555uc00 to fan53555uc08x, fan53555buc05x 2.000 0.03 1.600 0.03 0.20 0 0.200 option 1 fan53555buc08x, fan53555buc09x, fan53555uc09x, fan53555uc13x, fan53555buc13x, FAN53555UC18X, fan53555buc18x, fan53555buc23x, fan53555uc24x, fan53555buc24x, fan53555buc79x 2.015 0.03 1.615 0.03 0.2075 0.2075 option 2 omap is a trademark of texas instruments incorporated. novathor is a trademark of st ? ericsson sa. arm is a registered trademark of arm limited (or its subsidiaries) in the us and/or elsewhere.
wlcsp20 2.015x1.615x0.586 case 567qk issue o date 31 oct 201 6 mechanical case outline package dimensions http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: new standard: description: 98aon13330g on semiconductor standard wlcsp20 2.015x1.615x0.586 electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon13330g page 2 of 2 issue revision date o released for production from fairchild uc020aa to on semicon- ductor. req. by f. estrada. 31 oct 2016 ? semiconductor components industries, llc, 2016 october, 2016 ? rev. o case outline number : 567qk on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
wlcsp20 2.015x1.615x0.586 case 567sh issue o date 30 nov 201 6 mechanical case outline package dimensions http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: new standard: description: 98aon16602g on semiconductor standard wlcsp20 2.015x1.615x0.586 electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon16602g page 2 of 2 issue revision date o released for production from fairchild uc020aa to on semicon- ductor. req. by f. estrada. 30 nov 2016 ? semiconductor components industries, llc, 2016 november, 2016 ? rev. o case outline number : 567sh on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
wlcsp20 2.0x1.6x0.586 case 567sk issue o date 30 nov 201 6 mechanical case outline package dimensions http://onsemi.com 1 ? semiconductor components industries, llc, 2002 october, 2002 ? rev. 0 case outline number: xxx document number: status: new standard: description: 98aon16604g on semiconductor standard wlcsp20 2.0x1.6x0.586 electronic versions are uncontrolled except when accessed directly from the document repository. printed versions are uncontrolled except when stamped ?controlled copy? in red. page 1 of 2
document number: 98aon16604g page 2 of 2 issue revision date o released for production from fairchild uc020aa to on semicon- ductor. req. by f. estrada. 30 nov 2016 ? semiconductor components industries, llc, 2016 november, 2016 ? rev. o case outline number : 567sk on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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